<?php
/**
 * <https://y.st./>
 * Copyright © 2017 Alex Yst <mailto:copyright@y.st>
 * 
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program. If not, see <https://www.gnu.org./licenses/>.
**/

$xhtml = array(
	'<{title}>' => 'Circuits',
	'<{subtitle}>' => 'Written in <span title="Software Engineering 1">CS 2401</span>, finalised on 2017-11-29',
	'<{copyright year}>' => '2017',
	'takedown' => '2017-11-01',
	'<{body}>' => <<<END
<h2>Assignment 1</h2>
<img src="/img/CC_BY-SA_4.0/y.st./coursework/CS1104/alarm.png" alt="Alarm chip diagram" class="framed-centred-image" width="273" height="96"/>
<blockquote>
<pre><code>&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;
&lt;project source=&quot;2.7.1&quot; version=&quot;1.0&quot;&gt;
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
&lt;lib desc=&quot;#Wiring&quot; name=&quot;0&quot;/&gt;
  &lt;lib desc=&quot;#Gates&quot; name=&quot;1&quot;/&gt;
  &lt;lib desc=&quot;#Plexers&quot; name=&quot;2&quot;/&gt;
  &lt;lib desc=&quot;#Arithmetic&quot; name=&quot;3&quot;/&gt;
  &lt;lib desc=&quot;#Memory&quot; name=&quot;4&quot;/&gt;
  &lt;lib desc=&quot;#I/O&quot; name=&quot;5&quot;/&gt;
  &lt;lib desc=&quot;#Base&quot; name=&quot;6&quot;&gt;
    &lt;tool name=&quot;Text Tool&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
      &lt;a name=&quot;halign&quot; val=&quot;center&quot;/&gt;
      &lt;a name=&quot;valign&quot; val=&quot;base&quot;/&gt;
    &lt;/tool&gt;
  &lt;/lib&gt;
  &lt;main name=&quot;main&quot;/&gt;
  &lt;options&gt;
    &lt;a name=&quot;gateUndefined&quot; val=&quot;ignore&quot;/&gt;
    &lt;a name=&quot;simlimit&quot; val=&quot;1000&quot;/&gt;
    &lt;a name=&quot;simrand&quot; val=&quot;0&quot;/&gt;
  &lt;/options&gt;
  &lt;mappings&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Button2&quot; name=&quot;Menu Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Button3&quot; name=&quot;Menu Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Ctrl Button1&quot; name=&quot;Menu Tool&quot;/&gt;
  &lt;/mappings&gt;
  &lt;toolbar&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Poke Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Edit Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Text Tool&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
      &lt;a name=&quot;halign&quot; val=&quot;center&quot;/&gt;
      &lt;a name=&quot;valign&quot; val=&quot;base&quot;/&gt;
    &lt;/tool&gt;
    &lt;sep/&gt;
    &lt;tool lib=&quot;0&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/tool&gt;
    &lt;tool lib=&quot;0&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;facing&quot; val=&quot;west&quot;/&gt;
      &lt;a name=&quot;output&quot; val=&quot;true&quot;/&gt;
      &lt;a name=&quot;labelloc&quot; val=&quot;east&quot;/&gt;
    &lt;/tool&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;NOT Gate&quot;/&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;OR Gate&quot;/&gt;
  &lt;/toolbar&gt;
  &lt;circuit name=&quot;main&quot;&gt;
    &lt;a name=&quot;circuit&quot; val=&quot;main&quot;/&gt;
    &lt;a name=&quot;clabel&quot; val=&quot;&quot;/&gt;
    &lt;a name=&quot;clabelup&quot; val=&quot;east&quot;/&gt;
    &lt;a name=&quot;clabelfont&quot; val=&quot;SansSerif plain 12&quot;/&gt;
    &lt;wire from=&quot;(290,150)&quot; to=&quot;(300,150)&quot;/&gt;
    &lt;wire from=&quot;(170,170)&quot; to=&quot;(180,170)&quot;/&gt;
    &lt;wire from=&quot;(170,150)&quot; to=&quot;(180,150)&quot;/&gt;
    &lt;wire from=&quot;(170,190)&quot; to=&quot;(180,190)&quot;/&gt;
    &lt;wire from=&quot;(230,170)&quot; to=&quot;(240,170)&quot;/&gt;
    &lt;wire from=&quot;(170,130)&quot; to=&quot;(240,130)&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(290,150)&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,130)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(230,170)&quot; name=&quot;OR Gate&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,150)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,190)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;6&quot; loc=&quot;(127,197)&quot; name=&quot;Text&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;Motion&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,170)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;6&quot; loc=&quot;(124,134)&quot; name=&quot;Text&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;Armed&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;6&quot; loc=&quot;(121,155)&quot; name=&quot;Text&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;Door&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;6&quot; loc=&quot;(343,155)&quot; name=&quot;Text&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;Alarm&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(300,150)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;facing&quot; val=&quot;west&quot;/&gt;
      &lt;a name=&quot;output&quot; val=&quot;true&quot;/&gt;
      &lt;a name=&quot;labelloc&quot; val=&quot;east&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;6&quot; loc=&quot;(123,177)&quot; name=&quot;Text&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;Glass&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;Monospaced plain 12&quot;/&gt;
    &lt;/comp&gt;
  &lt;/circuit&gt;
&lt;/project&gt;</code></pre>
</blockquote>
<h2>Assignment 2</h2>
<table>
	<thead>
		<tr>
			<th>
				A
			</th>
			<th>
				B
			</th>
			<th>
				C
			</th>
			<th>
				X
			</th>
		</tr>
	</thead>
	<tbody>
		<tr>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
		</tr>
	</tbody>
</table>
<h2>Assignment 3</h2>
<p>
	There are two definitions of what a xor gate does.
	By one definition, it outputs <code>1</code> if and only if exactly one input is <code>1</code>.
	It outputs <code>0</code> otherwise.
	This is the definition used by Logisim.
	By the other definition, a xor gate outputs <code>1</code> if and only if the number of <code>1</code>-valued inputs is even.
	The textbook uses this definition.
	The truth is that n-input xor is ill-defined when n is not equal to two.
	For other values of n, the concept of an n-input xor gate is ambiguous.
	For this assignment, we are supposed to build a truth table and circuit design for a three-input xnor gate, but xnor is the complement of xor.
	Because the concept of a three-input xor gate is ill-defined and ambiguous, so is the concept of a three-input xnor gate.
	For completeness, I&apos;ll show the truth table and build a gate for each of the two definitions of a three-input xnor gate.
</p>
<h3>Book version</h3>
<p>
	By the book&apos;s definition, a xor gate checks to see if its input is even.
	That means its complement, the xnor gate, checks to see that it&apos;s input is odd.
	It&apos;s worth noting that this definition of xor doesn&apos;t really fit the phrase &quot;exclusive or&quot;, because it returns true in some cases when none of the inputs were the exclusive one to input true.
</p>
<table>
	<thead>
		<tr>
			<th>
				A
			</th>
			<th>
				B
			</th>
			<th>
				C
			</th>
			<th>
				X
			</th>
		</tr>
	</thead>
	<tbody>
		<tr>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
	</tbody>
</table>
<p>
	The premise of my design was to construct a two-input xnor gate, feed the first two inputs into it, then feed the output of that constructed two-input xnor gate along with the third input into a second constructed two-input xnor gate.
</p>
<img src="/img/CC_BY-SA_4.0/y.st./coursework/CS1104/odd_value_checker.png" alt="Odd value checker" class="framed-centred-image" width="230" height="240"/>
<blockquote>
<pre><code>&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;
&lt;project source=&quot;2.7.1&quot; version=&quot;1.0&quot;&gt;
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
&lt;lib desc=&quot;#Wiring&quot; name=&quot;0&quot;/&gt;
  &lt;lib desc=&quot;#Gates&quot; name=&quot;1&quot;/&gt;
  &lt;lib desc=&quot;#Plexers&quot; name=&quot;2&quot;/&gt;
  &lt;lib desc=&quot;#Arithmetic&quot; name=&quot;3&quot;/&gt;
  &lt;lib desc=&quot;#Memory&quot; name=&quot;4&quot;/&gt;
  &lt;lib desc=&quot;#I/O&quot; name=&quot;5&quot;/&gt;
  &lt;lib desc=&quot;#Base&quot; name=&quot;6&quot;&gt;
    &lt;tool name=&quot;Text Tool&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;SansSerif plain 12&quot;/&gt;
      &lt;a name=&quot;halign&quot; val=&quot;center&quot;/&gt;
      &lt;a name=&quot;valign&quot; val=&quot;base&quot;/&gt;
    &lt;/tool&gt;
  &lt;/lib&gt;
  &lt;main name=&quot;main&quot;/&gt;
  &lt;options&gt;
    &lt;a name=&quot;gateUndefined&quot; val=&quot;ignore&quot;/&gt;
    &lt;a name=&quot;simlimit&quot; val=&quot;1000&quot;/&gt;
    &lt;a name=&quot;simrand&quot; val=&quot;0&quot;/&gt;
  &lt;/options&gt;
  &lt;mappings&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Button2&quot; name=&quot;Menu Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Button3&quot; name=&quot;Menu Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Ctrl Button1&quot; name=&quot;Menu Tool&quot;/&gt;
  &lt;/mappings&gt;
  &lt;toolbar&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Poke Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Edit Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Text Tool&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;SansSerif plain 12&quot;/&gt;
      &lt;a name=&quot;halign&quot; val=&quot;center&quot;/&gt;
      &lt;a name=&quot;valign&quot; val=&quot;base&quot;/&gt;
    &lt;/tool&gt;
    &lt;sep/&gt;
    &lt;tool lib=&quot;0&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/tool&gt;
    &lt;tool lib=&quot;0&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;facing&quot; val=&quot;west&quot;/&gt;
      &lt;a name=&quot;output&quot; val=&quot;true&quot;/&gt;
      &lt;a name=&quot;labelloc&quot; val=&quot;east&quot;/&gt;
    &lt;/tool&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;NOT Gate&quot;/&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;OR Gate&quot;/&gt;
  &lt;/toolbar&gt;
  &lt;circuit name=&quot;main&quot;&gt;
    &lt;a name=&quot;circuit&quot; val=&quot;main&quot;/&gt;
    &lt;a name=&quot;clabel&quot; val=&quot;&quot;/&gt;
    &lt;a name=&quot;clabelup&quot; val=&quot;east&quot;/&gt;
    &lt;a name=&quot;clabelfont&quot; val=&quot;SansSerif plain 12&quot;/&gt;
    &lt;wire from=&quot;(200,120)&quot; to=&quot;(200,130)&quot;/&gt;
    &lt;wire from=&quot;(200,240)&quot; to=&quot;(200,250)&quot;/&gt;
    &lt;wire from=&quot;(280,150)&quot; to=&quot;(280,170)&quot;/&gt;
    &lt;wire from=&quot;(280,110)&quot; to=&quot;(280,130)&quot;/&gt;
    &lt;wire from=&quot;(280,230)&quot; to=&quot;(280,250)&quot;/&gt;
    &lt;wire from=&quot;(280,270)&quot; to=&quot;(280,290)&quot;/&gt;
    &lt;wire from=&quot;(190,220)&quot; to=&quot;(190,300)&quot;/&gt;
    &lt;wire from=&quot;(190,200)&quot; to=&quot;(190,220)&quot;/&gt;
    &lt;wire from=&quot;(190,160)&quot; to=&quot;(190,180)&quot;/&gt;
    &lt;wire from=&quot;(200,130)&quot; to=&quot;(200,160)&quot;/&gt;
    &lt;wire from=&quot;(200,250)&quot; to=&quot;(200,280)&quot;/&gt;
    &lt;wire from=&quot;(170,130)&quot; to=&quot;(200,130)&quot;/&gt;
    &lt;wire from=&quot;(190,200)&quot; to=&quot;(350,200)&quot;/&gt;
    &lt;wire from=&quot;(260,290)&quot; to=&quot;(280,290)&quot;/&gt;
    &lt;wire from=&quot;(190,100)&quot; to=&quot;(210,100)&quot;/&gt;
    &lt;wire from=&quot;(190,180)&quot; to=&quot;(210,180)&quot;/&gt;
    &lt;wire from=&quot;(190,220)&quot; to=&quot;(210,220)&quot;/&gt;
    &lt;wire from=&quot;(180,250)&quot; to=&quot;(200,250)&quot;/&gt;
    &lt;wire from=&quot;(170,160)&quot; to=&quot;(190,160)&quot;/&gt;
    &lt;wire from=&quot;(260,110)&quot; to=&quot;(280,110)&quot;/&gt;
    &lt;wire from=&quot;(190,300)&quot; to=&quot;(210,300)&quot;/&gt;
    &lt;wire from=&quot;(270,170)&quot; to=&quot;(280,170)&quot;/&gt;
    &lt;wire from=&quot;(280,150)&quot; to=&quot;(290,150)&quot;/&gt;
    &lt;wire from=&quot;(280,130)&quot; to=&quot;(290,130)&quot;/&gt;
    &lt;wire from=&quot;(270,230)&quot; to=&quot;(280,230)&quot;/&gt;
    &lt;wire from=&quot;(280,250)&quot; to=&quot;(290,250)&quot;/&gt;
    &lt;wire from=&quot;(280,270)&quot; to=&quot;(290,270)&quot;/&gt;
    &lt;wire from=&quot;(340,140)&quot; to=&quot;(350,140)&quot;/&gt;
    &lt;wire from=&quot;(340,260)&quot; to=&quot;(350,260)&quot;/&gt;
    &lt;wire from=&quot;(170,190)&quot; to=&quot;(180,190)&quot;/&gt;
    &lt;wire from=&quot;(200,120)&quot; to=&quot;(210,120)&quot;/&gt;
    &lt;wire from=&quot;(200,160)&quot; to=&quot;(210,160)&quot;/&gt;
    &lt;wire from=&quot;(200,240)&quot; to=&quot;(210,240)&quot;/&gt;
    &lt;wire from=&quot;(200,280)&quot; to=&quot;(210,280)&quot;/&gt;
    &lt;wire from=&quot;(350,140)&quot; to=&quot;(350,200)&quot;/&gt;
    &lt;wire from=&quot;(180,190)&quot; to=&quot;(180,250)&quot;/&gt;
    &lt;wire from=&quot;(190,100)&quot; to=&quot;(190,160)&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(260,290)&quot; name=&quot;OR Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(340,260)&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(340,140)&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(260,110)&quot; name=&quot;OR Gate&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,160)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(350,260)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;facing&quot; val=&quot;west&quot;/&gt;
      &lt;a name=&quot;output&quot; val=&quot;true&quot;/&gt;
      &lt;a name=&quot;labelloc&quot; val=&quot;east&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(270,170)&quot; name=&quot;NAND Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(270,230)&quot; name=&quot;NAND Gate&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,130)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(170,190)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
  &lt;/circuit&gt;
&lt;/project&gt;</code></pre>
</blockquote>
<h3>Logisim version</h3>
<p>
	By Logisim&apos;s definition, a xor gate returns <code>1</code> if and only if one of it&apos;s inputs was exclusively the one to input <code>1</code>.
	If multiple inputs feed in <code>1</code> or if no inputs feed in <code>1</code>, Logisim&apos;s xor will return <code>0</code>.
	This definition of xor lives up to its name.
	Its complement, xnor, therefore outputs <code>0</code> any time exactly one input feeds in <code>1</code>, and returns <code>1</code> if zero, two, or more than two inputs feed in <code>1</code>.
</p>
<table>
	<thead>
		<tr>
			<th>
				A
			</th>
			<th>
				B
			</th>
			<th>
				C
			</th>
			<th>
				X
			</th>
		</tr>
	</thead>
	<tbody>
		<tr>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
			<td>
				0
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				0
			</td>
			<td>
				1
			</td>
		</tr>
		<tr>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
			<td>
				1
			</td>
		</tr>
	</tbody>
</table>
<p>
	The premise of my design on this one is simpler.
	If all inputs are <code>0</code>, return <code>1</code>.
	If any two (or more) inputs are <code>1</code>, return <code>1</code>.
	Otherwise, exactly one input is <code>1</code>, so return <code>0</code>.
</p>
<img src="/img/CC_BY-SA_4.0/y.st./coursework/CS1104/inverted_xor.png" alt="Inverted xor" class="framed-centred-image" width="250" height="240"/>
<blockquote>
<pre><code>&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;
&lt;project source=&quot;2.7.1&quot; version=&quot;1.0&quot;&gt;
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
&lt;lib desc=&quot;#Wiring&quot; name=&quot;0&quot;/&gt;
  &lt;lib desc=&quot;#Gates&quot; name=&quot;1&quot;/&gt;
  &lt;lib desc=&quot;#Plexers&quot; name=&quot;2&quot;/&gt;
  &lt;lib desc=&quot;#Arithmetic&quot; name=&quot;3&quot;/&gt;
  &lt;lib desc=&quot;#Memory&quot; name=&quot;4&quot;/&gt;
  &lt;lib desc=&quot;#I/O&quot; name=&quot;5&quot;/&gt;
  &lt;lib desc=&quot;#Base&quot; name=&quot;6&quot;&gt;
    &lt;tool name=&quot;Text Tool&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;SansSerif plain 12&quot;/&gt;
      &lt;a name=&quot;halign&quot; val=&quot;center&quot;/&gt;
      &lt;a name=&quot;valign&quot; val=&quot;base&quot;/&gt;
    &lt;/tool&gt;
  &lt;/lib&gt;
  &lt;main name=&quot;main&quot;/&gt;
  &lt;options&gt;
    &lt;a name=&quot;gateUndefined&quot; val=&quot;ignore&quot;/&gt;
    &lt;a name=&quot;simlimit&quot; val=&quot;1000&quot;/&gt;
    &lt;a name=&quot;simrand&quot; val=&quot;0&quot;/&gt;
  &lt;/options&gt;
  &lt;mappings&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Button2&quot; name=&quot;Menu Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Button3&quot; name=&quot;Menu Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; map=&quot;Ctrl Button1&quot; name=&quot;Menu Tool&quot;/&gt;
  &lt;/mappings&gt;
  &lt;toolbar&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Poke Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Edit Tool&quot;/&gt;
    &lt;tool lib=&quot;6&quot; name=&quot;Text Tool&quot;&gt;
      &lt;a name=&quot;text&quot; val=&quot;&quot;/&gt;
      &lt;a name=&quot;font&quot; val=&quot;SansSerif plain 12&quot;/&gt;
      &lt;a name=&quot;halign&quot; val=&quot;center&quot;/&gt;
      &lt;a name=&quot;valign&quot; val=&quot;base&quot;/&gt;
    &lt;/tool&gt;
    &lt;sep/&gt;
    &lt;tool lib=&quot;0&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/tool&gt;
    &lt;tool lib=&quot;0&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;facing&quot; val=&quot;west&quot;/&gt;
      &lt;a name=&quot;output&quot; val=&quot;true&quot;/&gt;
      &lt;a name=&quot;labelloc&quot; val=&quot;east&quot;/&gt;
    &lt;/tool&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;NOT Gate&quot;/&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;tool lib=&quot;1&quot; name=&quot;OR Gate&quot;/&gt;
  &lt;/toolbar&gt;
  &lt;circuit name=&quot;main&quot;&gt;
    &lt;a name=&quot;circuit&quot; val=&quot;main&quot;/&gt;
    &lt;a name=&quot;clabel&quot; val=&quot;&quot;/&gt;
    &lt;a name=&quot;clabelup&quot; val=&quot;east&quot;/&gt;
    &lt;a name=&quot;clabelfont&quot; val=&quot;SansSerif plain 12&quot;/&gt;
    &lt;wire from=&quot;(290,100)&quot; to=&quot;(290,170)&quot;/&gt;
    &lt;wire from=&quot;(290,210)&quot; to=&quot;(290,280)&quot;/&gt;
    &lt;wire from=&quot;(170,90)&quot; to=&quot;(170,160)&quot;/&gt;
    &lt;wire from=&quot;(190,220)&quot; to=&quot;(190,230)&quot;/&gt;
    &lt;wire from=&quot;(200,150)&quot; to=&quot;(200,160)&quot;/&gt;
    &lt;wire from=&quot;(170,90)&quot; to=&quot;(220,90)&quot;/&gt;
    &lt;wire from=&quot;(280,160)&quot; to=&quot;(280,180)&quot;/&gt;
    &lt;wire from=&quot;(280,200)&quot; to=&quot;(280,220)&quot;/&gt;
    &lt;wire from=&quot;(210,190)&quot; to=&quot;(210,270)&quot;/&gt;
    &lt;wire from=&quot;(210,170)&quot; to=&quot;(210,190)&quot;/&gt;
    &lt;wire from=&quot;(180,100)&quot; to=&quot;(180,190)&quot;/&gt;
    &lt;wire from=&quot;(180,100)&quot; to=&quot;(220,100)&quot;/&gt;
    &lt;wire from=&quot;(160,220)&quot; to=&quot;(190,220)&quot;/&gt;
    &lt;wire from=&quot;(170,160)&quot; to=&quot;(200,160)&quot;/&gt;
    &lt;wire from=&quot;(180,190)&quot; to=&quot;(210,190)&quot;/&gt;
    &lt;wire from=&quot;(190,110)&quot; to=&quot;(220,110)&quot;/&gt;
    &lt;wire from=&quot;(190,290)&quot; to=&quot;(220,290)&quot;/&gt;
    &lt;wire from=&quot;(190,230)&quot; to=&quot;(220,230)&quot;/&gt;
    &lt;wire from=&quot;(280,180)&quot; to=&quot;(300,180)&quot;/&gt;
    &lt;wire from=&quot;(280,200)&quot; to=&quot;(300,200)&quot;/&gt;
    &lt;wire from=&quot;(270,280)&quot; to=&quot;(290,280)&quot;/&gt;
    &lt;wire from=&quot;(190,110)&quot; to=&quot;(190,220)&quot;/&gt;
    &lt;wire from=&quot;(160,190)&quot; to=&quot;(180,190)&quot;/&gt;
    &lt;wire from=&quot;(200,210)&quot; to=&quot;(220,210)&quot;/&gt;
    &lt;wire from=&quot;(200,150)&quot; to=&quot;(220,150)&quot;/&gt;
    &lt;wire from=&quot;(200,160)&quot; to=&quot;(200,210)&quot;/&gt;
    &lt;wire from=&quot;(270,160)&quot; to=&quot;(280,160)&quot;/&gt;
    &lt;wire from=&quot;(270,220)&quot; to=&quot;(280,220)&quot;/&gt;
    &lt;wire from=&quot;(280,100)&quot; to=&quot;(290,100)&quot;/&gt;
    &lt;wire from=&quot;(290,170)&quot; to=&quot;(300,170)&quot;/&gt;
    &lt;wire from=&quot;(290,210)&quot; to=&quot;(300,210)&quot;/&gt;
    &lt;wire from=&quot;(350,190)&quot; to=&quot;(360,190)&quot;/&gt;
    &lt;wire from=&quot;(160,160)&quot; to=&quot;(170,160)&quot;/&gt;
    &lt;wire from=&quot;(210,270)&quot; to=&quot;(220,270)&quot;/&gt;
    &lt;wire from=&quot;(210,170)&quot; to=&quot;(220,170)&quot;/&gt;
    &lt;wire from=&quot;(190,230)&quot; to=&quot;(190,290)&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(360,190)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;facing&quot; val=&quot;west&quot;/&gt;
      &lt;a name=&quot;output&quot; val=&quot;true&quot;/&gt;
      &lt;a name=&quot;labelloc&quot; val=&quot;east&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(160,220)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(270,220)&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(160,190)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(270,160)&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(280,100)&quot; name=&quot;NOR Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(350,190)&quot; name=&quot;OR Gate&quot;/&gt;
    &lt;comp lib=&quot;1&quot; loc=&quot;(270,280)&quot; name=&quot;AND Gate&quot;/&gt;
    &lt;comp lib=&quot;0&quot; loc=&quot;(160,160)&quot; name=&quot;Pin&quot;&gt;
      &lt;a name=&quot;tristate&quot; val=&quot;false&quot;/&gt;
    &lt;/comp&gt;
  &lt;/circuit&gt;
&lt;/project&gt;</code></pre>
</blockquote>
END
);
